The basic arrangement of a typical microprocessor based computer system is well known. Connected to a common system data bus are a microprocessor, various types of memory, peripheral input/output circuits, and the like. In addition to being commonly connected by the system data bus, a number of control and status lines also interconnect the circuit elements. The microprocessor communicates with all these system circuits, one at a time.
A popular and widely used microprocessor system is a family of Z80.RTM. brand components marketed by Zilog, Inc. of Campbell, Calif., assignee of the present application. In order to reduce hardware interconnections between a microprocessor chip and a number of peripheral input/output chips that might be utilized in a given system, the Z80 system contemplates connecting the peripheral circuit chips with each other and the microprocessor by use of a daisy chain interrupt circuit scheme. This system prioritizes the various peripherals in order to resolve competing interrupt requests from two or more of them. The microprocessor, of course, can service only one peripheral at a time. A detailed technical discussion of the Z80 microprocessor and peripherals is set forth in a book entitled "Z80 Family Data Book", dated January 1989, available from Zilog, Inc. The Z80 family components interrupt structure, including the daisy-chained interconnection of Z80 peripherals, is described at pages 293-304 of this book.
In such a peripheral connection system, there is an inherent propagation delay of an interrupt enable signal through the daisy chain circuit. When the Z80 system was first introduced many years ago, the microprocessor was operated at a slow enough clock speed that its multiple clock period machine cycles were long enough to allow sufficient time for this signal to propagate along the entire peripheral daisy chain circuit during such cycles. This is required for certain peripheral interrupt acknowledge and return from interrupt communications between the microprocessor and a selected peripheral.
However, in more recent times, clock speeds increased and the same microprocessor machine cycles are accomplished in a much shorter period of time while the propagation delay of a given daisy-chained peripheral circuit has not been reduced by the same proportion. As a result, a problem in acknowledging an interrupt request from a peripheral was noted in certain situations. If the highest priority peripheral issues an interrupt request, at the beginning portion of the microprocessor interrupt acknowledge machine cycle that is in response to an interrupt signal issued by the lowest priority peripheral, enough time must be provided in the interrupt acknowledge machine cycle to allow a logic low interrupt enable signal of the highest priority peripheral to travel the full length of the chain and inhibit the lowest priority peripheral from thinking that the interrupt acknowledge machine cycle issued by the microprocessor is for it. One of the methods to resolve this problem is to add a circuit that inserts one or more wait states in the interrupt acknowledge machine cycle to delay the active edge of the microprocessor control signal IORQ, as described on pages 300 and 301 of the Zilog book cited above.
More recently, with microprocessor speeds increasing even further, it has been found that a return from interrupt (RETI) operation can require more time to effect than allowed during a microprocessor opcode fetch machine cycle, depending upon the type and number of peripherals that are daisy-chained together. A logic high signal must propagate completely down the daisy chain during that machine cycle in order to assure that the correct one peripheral is enabled to act upon the RETI instruction.
It is an object of the present invention to provide a technique and circuit for solving such a timing problem in a straightforward and simple way that does not compromise operation of the system.